1. Field of Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a fabricating method of a dynamic random access memory (DRAM).
2. Description of Related Art
Two of the important strategies in the semiconductor industry are increasing the device's performance and decreasing the process cost. With the trend toward high integration density, the size of the DRAM capacitor must be further decreased. As the size of the DRAM capacitor decreases, the quality of the capacitor may also decrease. For example, as the DRAM size is decreased, the resistance effect becomes serious enough to reduce the device's performance.
It is important to decrease the device size in the DRAM manufacture processes. Typically, a DRAM includes a transfer transistor and a capacitor. The capacitor is electrically coupled with a source/drain region. A bit line, which comes from an isolation layer, is electrically coupled with the surface of the source/drain region through a contact hole.
FIG. 1 is a top view of a layout of a conventional DRAM. FIG. 2A is a cross-sectional view of a portion of the conventional DRAM of FIG. 1 taken along line I--I. FIG. 2B is a cross-sectional view of a portion of the conventional DRAM of FIG. 1 taken along line II--II.
In FIGS. 1 through 2B, a semiconductor substrate 10 is provided. An active region 12 is defined on the substrate 100. A transistor 22 is formed on the active region 12. The transistor 22 includes a gate 20 and a source/drain region 18. A first dielectric layer 24 is formed on the transistor 22. A second dielectric layer 26 is formed on the first dielectric layer 24. A bit line 16 is formed in the first dielectric layer 24 and the second dielectric layer 26. A photoresist layer 28 is formed on the second dielectric layer 26. A node contact 14 is formed in the first dielectric layer 24 and the second dielectric layer 26. The source/drain region 14 is electrically coupled with a capacitor (not shown) through the node contact 14.
The bit line 16 must be separated from the node contact 14. (Shown in FIG. 1) In the layout of the DRAM, when viewed from the top, the bit line 16 cannot overlap with the node contact 14. This separation prevents the bit line 16 from shorting with the node contact. Unfortunately, the bit line 16 and the node contact 14 cannot overlap in the layout, the downsizing of the DRAM components is limited.